1. Field of the Invention
The invention relates to an error correction circuit and method, and particularly to an error correction circuit and method for a DisplayPort receiver in order to improve the reliability of input data.
2. Description of the Related Art
DisplayPort is a new digital display interface standard put forth by the Video Electronics Standard Association (VESA), including a Main Link, an auxiliary channel (AUX CH), and a hot plug detect (HPD) signal line. Main Link is a high-bandwidth, low-latency, uni-directional interface used for transport of isochronous streams. The number of lanes of Main Link can be either 1, 2, or 4 lanes, providing digital video and audio for simultaneous streaming transmission. Each lane supports transmission at two link rates (Flink): 1.62 Gbps or 2.7 Gbps per lane. Therefore, DisplayPort offers up to 10.8 Gbps of bandwidth.
A DisplayPort transmitter uses a PCI-EXPRESS-like link to send send image data and audio data together with a high speed link clock (having the link rates Flink) and encodes 8-bit data signals and 8-bit control signals into 10-bit dc-balanced signals by a ANSI 8B/10B encoder. Reversely, a displayPort receiver uses a decoder to recover the 8-bit data signal and the 8-bit control signal. However, poor channel quality may result in erroneous received signals. Under such circumstances, corresponding original values are not found correctly at a decoding stage, making subsequent data to be determined incorrectly.
FIG. 1 is an example showing a main video stream data packing over 4-lane Main Link. Referring to FIG. 1, Main Link consists of four lanes L0˜L3. In terms of each of the four lanes L0˜L3, a video data area follows a blanking end (BE) signal, whereas a blanking start (BS) signal is inserted immediately after the video data area. Further, a VB-ID signal, a video time stamp value Mvid 7:0, an audio time stamp value Maud 7:0 and audio data are inserted between the signals BS and BE. Errors generated in the video data area may cause incorrect pixel values displayed in a frame. If an error is included in one of the control signals such as the signals BS, BE and VB-ID, several important image control signals such as a vertical synchronization (VS) signal and a horizontal synchronization (HS) signal may not be constructed correctly in the receivers.